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MC10H641, MC100H641 Single Supply PECL to TTL 1:9 Clock Distribution Chip
Description
The MC10H/100H641 is a single supply, low skew translating 1:9 clock driver. Devices in the ON Semiconductor H641 translator series utilize the PLCC-28 for optimal power pinning, signal flow through and electrical performance. The device features a 24 mA TTL output stage, with AC performance specified into a 50 pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. Both the LEN and EN pins are positive ECL inputs. The VBB output is provided in case the user wants to drive the device with a single-ended input. For single-ended use, the VBB should be connected to the D input and bypassed with a 0.01 mF capacitor. The 10H version of the H641 is compatible with positive MECL 10HTM logic levels. The 100H version is compatible with positive 100K levels.
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
* * * * * * * * * * *
PECL - TTL Version of Popular ECLinPS E111 Low Skew Guaranteed Skew Spec Latched Input Differential ECL Internal Design VBB Output for Single-Ended Use Single +5.0 V Supply Logic Enable Extra Power and Ground Supplies Separate ECL and TTL Supply Pins Pb-Free Packages are Available*
MCxxxH641G AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev.7
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Publication Order Number: MC10H641/D
MC10H641, MC100H641
GT 25 GT Q5 VT Q4 VT Q3 GT 26 27 28 1 2 3 4 5 GT 6 Q2 7 VT 8 Q1 9 VT 10 Q0 11 GT Q6 24 VT 23 Q7 22 VT 21 Q8 20 GT 19 18 17 16 15 14 13 12 VBB D D VE LEN GE EN
Table 1. PIN DESCRIPTION
Pins GT, VT GE, VE D, D VBB Q0 - Q8 EN LEN Function TTL GND, TTL VCC ECL GND, ECL VCC Signal Input (Positive ECL) VBB Reference Output (Positive ECL) Signal Outputs (TTL) Enable Input (Positive ECL) Latch Enable Input (Positive ECL)
Figure 1. Pinout: PLCC-28 (Top View)
TTL Outputs
Q0 Q1 Q2 Q3 DQ Q4 Q5 Q6 Q7 Q8
PECL Input
D D VBB LEN EN
Figure 2. Logic Diagram
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MC10H641, MC100H641
Table 2. 10H PECL DC CHARACTERISTICS
0C Symbol IINH IIL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V (Note 1) VE = 5.0 V (Note 1) VE = 5.0 V (Note 1) 0.5 3.83 3.05 3.62 4.16 3.52 3.73 Condition Min Max 255 0.5 3.87 3.05 3.65 4.19 3.52 3.75 25C Min Max 175 0.5 3.94 3.05 3.69 4.28 3.55 3.81 85C Min Max 175 Unit mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.
Table 3. 100H PECL DC CHARACTERISTICS
0C Symbol IINH IINL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V (Note 2) VE = 5.0 V (Note 2) VE = 5.0 V (Note 2) 0.5 3.835 3.190 3.62 4.120 3.525 3.74 Condition Min Max 255 0.5 3.835 3.190 3.62 4.120 3.525 3.74 25C Min Max 175 0.5 3.835 3.190 3.62 4.120 3.525 3.74 85C Min Max 175 Unit mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.
Table 4. DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
TA = 0C Symbol IEE ICCH ICCL Characteristic Power Supply Current PECL TTL Min Typ 24 24 27 Max 30 30 35 TA = + 25C Min Typ 24 24 27 Max 30 30 35 TA = + 85C Min Typ 24 24 27 Max 30 30 35 Unit mA mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol VOH VOL IOS Characteristic Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Condition IOH = -15 mA IOL = 24 mA VOUT = 0 V -100 Min 2.5 0.5 -225 -100 Max 25C Min 2.5 0.5 -225 -100 Max 85C Min 2.5 0.5 -225 Max Unit V V mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H641, MC100H641
Table 6. AC CHARACTERISTICS (VT = VE = 5.0 V 5%)
TJ = 0C Symbol tPLH tPHL tskew Characteristic Propagation Delay D to Q Device Skew Part-to-Part Single VCC Output-to-Output Condition CL = 50 pF (Note 3) Min 5.00 5.36 Typ 5.50 5.86 Max 6.00 6.36 1000 750 350 4.9 5.0 6.9 7.0 1.7 1.6 65 0.75 0.75 0.50 0.50 65 0.75 0.75 0.50 0.50 4.9 4.9 TJ = + 25C Min 4.86 5.27 Typ 5.36 5.77 Max 5.86 6.27 1000 750 350 6.9 6.9 1.7 1.6 65 0.75 0.75 0.50 0.50 5.0 5.0 TJ = + 85C Min 5.08 5.43 Typ 5.58 5.93 Max 6.08 6.43 1000 750 350 7.0 7.0 1.7 1.6 Unit ns ps
CL = 50 pF (Note 4) CL = 50 pF (Note 5) CL = 50 pF (Note 6) CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF (Note 7)
tPLH tPHL tPLH tPHL tr tf fMAX tS tH
Propagation Delay LEN to Q Propagation Delay EN to Q Output Rise/Fall 0.8 V to 2.0 V Max Input Frequency Setup Time Hold Time
ns ns ns MHz ns ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50 MHz input frequency. 4. Skew window guaranteed for a single temperature across a VCC = VT = VE of 4.75 V to 5.25 V (See Application Note in this data sheet). 5. Skew window guaranteed for a single temperature and single VCC = VT = VE 6. Output-to-output skew is specified for identical transitions through the device. 7. Frequency at which output levels will meet a 0.8 V to 2.0 V minimum swing.
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MC10H641, MC100H641
Determining Skew for a Specific Application The H641 has been designed to meet the needs of very low skew clock distribution applications. In order to optimize the device for this application special considerations are necessary in the determining of the part-to-part skew specification limits. Older standard logic devices are specified with relatively slack limits so that the device can be guaranteed over a wide range of potential environmental conditions. This range of conditions represented all of the potential applications in which the device could be used. The result was a specification limit that in the vast majority of cases was extremely conservative and thus did not allow for an optimum system design. For non-critical skew designs this practice is acceptable, however as the clock speeds of systems increase overly conservative specification limits can kill a design. The following will discuss how users can use the information provided in this data sheet to tailor a part-to-part skew specification limit to their application. The skew determination process may appear somewhat tedious and time consuming, however if the utmost in performance is required this procedure is necessary. For applications which do not require this level of skew performance a generic part-to-part skew limit of 2.5 ns can be used. This limit is good for the entire ambient temperature range, the guaranteed VCC (VT, VE) range and the guaranteed operating frequency range.
Temperature Dependence
PD (watts) = ICC (no load) * VCC + VS * VCC * f * CL * # Outputs where: VS= Output Voltage Swing = 3.0 V f = Output Frequency CL = Load Capacitance ICC = IEE + ICCH Figure 1 plots the ICC versus Frequency of the H641 with no load capacitance on the output. Using this graph and the information specific to the application a user can determine the power dissipation of the H641.
5
4 NORMALIZED ICC
3
2
1
0
0
10
20
30
40
50
60
70
80
A unique characteristic of the H641 data sheet is that the AC parameters are specified for a junction temperature rather than the usual ambient temperature. Because very few designs will actually utilize the entire commercial temperature range of a device a tighter propagation delay window can be established given the smaller temperature range. Because the junction temperature and not the ambient temperature is what affects the performance of the device the parameter limits are specified for junction temperature. In addition the relationship between the ambient and junction temperature will vary depending on the frequency, load and board environment of the application. Since these factors are all under the control of the user it is impossible to provide specification limits for every possible application. Therefore a baseline specification was established for specific junction temperatures and the information that follows will allow these to be tailored to specific applications. Since the junction temperature of a device is difficult to measure directly, the first requirement is to be able to "translate" from ambient to junction temperatures. The standard method of doing this is to use the power dissipation of the device and the thermal resistance of the package. For a TTL output device the power dissipation will be a function of the load capacitance and the frequency of the output. The total power dissipation of a device can be described by the following equation:
FREQUENCY (MHz)
Figure 2 illustrates the thermal resistance (in C/W) for the PLCC-28 under various air flow conditions. By reading the thermal resistance from the graph and multiplying by the power dissipation calculated above the junction temperature increase above ambient of the device can be calculated.
70
Figure 1. ICC versus f (No Load)
THERMAL RESISTANCE (C/W)
60
50
40
30
0
200
400
600
800
1000
AIRFLOW (LFPM)
Figure 2. jJA versus Air Flow
Finally taking this value for junction temperature and applying it to Figure 3 allows the user to determine the
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MC10H641, MC100H641
propagation delay for the device in question. A more common use would be to establish an ambient temperature range for the H641's in the system and utilize the above methodology to determine the potential increased skew of the distribution network. Note that for this information if the TPD versus Temperature curve were linear the calculations would not be required. If the curve were linear over all temperatures a simple temperature coefficient could be provided.
6.4
propagation delay at the typical, minimum and maximum VCC.
140 100 60 TPD (ps) 20 -20 -60 -100 -140 4.75 TPHL TPLH
6.2 PROPAGATION DELAY (ns)
TPHL
6.0
5.8 TPLH
4.85
4.95
5.05 VCC (V)
5.15
5.25
5.6
Figure 4. DTPD versus VCC Capacitive Load Dependence
5.4
5.2
-30
-10
10
30
50
70
90
110
130
Figure 3. TPD versus Junction Temperature
JUNCTION TEMPERATURE ( C)
MORMALIZED PROPAGATION DELAY (ns)
TTL and CMOS devices show a significant propagation delay dependence with VCC. Therefore the VCC variation in a system will have a direct impact on the total skew of the clock distribution network. When calculating the skew between two devices on a single board it is very likely an assumption of identical VCC's can be made. In this case the number provided in the data sheet for part-to-part skew would be overly conservative. By using Figure 4 the skew given in the data sheet can be reduced to represent a smaller or zero variation in VCC. The delay variation due to the specified VCC variation is 270 ps. Therefore, the 1 ns window on the data sheet can be reduced by 270 ps if the devices in question will always experience the same VCC. The distribution of the propagation delay ranges given in the data sheet is actually a composite of three distributions whose means are separated by the fixed difference in
VCC Dependence
As with VCC the propagation delay of a TTL output is intimately tied to variation in the load capacitance. The skew specifications given in the data sheet, of course, assume equal loading on all of the outputs. However situations could arise where this is an impossibility and it may be necessary to estimate the skew added by asymmetric loading. In addition the propagation delay numbers are provided only for 50 pF loads, thus necessitating a method of determining the propagation delay for alternative loads. Figure 5 shows the relationship between the two propagation delays with respect to the capacitive load on the output. Utilizing this graph and the 50 pF limits the specification of the H641 can be mapped into a spec for either a different value load or asymmetric loads.
1.15 1.10 1.05 1.00 0.95 0.90 TPHL 0.85 0.80 0.75 0 THEORETICAL 10 20 30 40 50 60 70 80 90 100 MEASURED TPLH
CAPACITIVE LOAD (pF)
Figure 5. TPD versus Load
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MC10H641, MC100H641
Rise/Fall Skew Determination
The rise-to-fall skew is defined as simply the difference between the TPLH and the TPHL propagation delays. This skew for the H641 is dependent on the VCC applied to the device. Notice from Figure 4 the opposite relationship of TPD versus VCC between TPLH and TPHL. Because of this the rise-to-fall skew will vary depending on VCC. Since in all likelihood it will be impossible to establish the exact value for VCC, the expected variation range for VCC should be used. If this variation will be the 5% shown in the data sheet the rise-to-fall skew could be established by simply subtracting the fastest TPLH from the slowest TPHL; this exercise yields 1.41 ns. If a tighter VCC range can be realized Figure 4 can be used to establish the rise-to-fall skew.
Specification Limit Determination Example
The situation pictured in Figure 6 will be analyzed as an example. The central clock is distributed to two different cards; on one card a single H641 is used to distribute the clock while on the second card two H641's are required to supply the needed clocks. The data sheet as well as the graphical information of this section will be used to calculate the skew between H641a and H641b as well as the skew between all three of the devices. Only the TPLH will be analyzed, the TPHL numbers can be found using the same technique. The following assumptions will be used: - All outputs will be loaded with 50 pF - All outputs will toggle at 30 MHz - The VCC variation between the two boards is 3 % - The temperature variation between the three devices is 15C around an ambient of 45C. - 500 lfpm air flow The first task is to calculate the junction temperature for the devices under these conditions. Using the power equation yields: PD = ICC (no load) * VCC + VCC * VS * f * CL * # outputs =4.3 * 48m A * 5.0 V + 5.0 V * 3.0 V * 30 MHz * 50 pF * 9 =432 mW + 203 mW = 635 mW Using the thermal resistance graph of Figure 2 yields a thermal resistance of 41C/W which yields a junction temperature of 71C with a range of 56C to 86C. Using the TPD versus Temperature curve of Figure 3 yields a propagation delay of 5.42 ns and a variation of 0.19 ns. Since the design will not experience the full 5% VCC variation of the data sheet the 1.0 ns window provided will be unnecessarily conservative. Using the curve of Figure 4 shows a delay variation due to a 3% VCC variation of 0.075 ns. Therefore the 1.0 ns window can be reduced to 1.0 ns - (0.27 ns - 0.15 ns) = 0.88 ns. Since H641a and H641b are on the same board we will assume that they will
always be at the same VCC; therefore the propagation delay window will only be 1 ns - 0.27 ns = 0.73 ns. Putting all of this information together leads to a skew between all devices of 0.19 ns + 0.88 ns (temperature + supply, and inherent device), while the skew between devices A and B will be only 0.19 ns + 0.73 ns (temperature + inherent device only). In both cases, the propagation delays will be centered around 5.42 ns, resulting in the following tPLH windows: TPLH = 4.92 ns - 5.99 ns; 1.07 ns window (all devices) TPLH= 5.00 ns - 5.92 ns; 0.92 ns window (devices a & b) Of course the output-to-output skew will be as shown in the data sheet since all outputs are equally loaded. This process may seem cumbersome, however the delay windows, and thus skew, obtained are significantly better than the conservative worst case limits provided at the beginning of this note. For very high performance designs, this extra information and effort can mean the difference between going ahead with prototypes or spending valuable engineering time searching for alternative approaches.
Card 1 H641a Q0 ECL Q8 TTL
H641b Q0 ECL BACKPLANE Q8 TTL
Card 2 H641c Q0 ECL Q8 TTL
Figure 6. Example Application
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MC10H641, MC100H641
ORDERING INFORMATION
Device MC10H641FN MC10H641FNG MC10H641FNR2 MC10H641FNR2G MC100H641FN MC100H641FNG MC100H641FNR2 MC100H641FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10H641, MC100H641
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10H641, MC100H641
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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